diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index ebd39cb41a..8568ba29d8 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -65,7 +65,7 @@ static inline bool supports_extension(char ext)
 #endif /* CONFIG_CPU */
 }
 
-static int riscv_cpu_probe(void)
+static int riscv_cpu_probe(void *ctx, struct event *event)
 {
 #ifdef CONFIG_CPU
 	int ret;
@@ -78,7 +78,7 @@ static int riscv_cpu_probe(void)
 
 	return 0;
 }
-EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, riscv_cpu_probe);
+EVENT_SPY_FULL(EVT_DM_POST_INIT_R, riscv_cpu_probe);
 
 /*
  * This is called on secondary harts just after the IPI is init'd. Currently
@@ -91,9 +91,13 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
 }
 #endif
 
-int riscv_cpu_setup(void)
+int riscv_cpu_setup(void *ctx, struct event *event)
 {
-	int __maybe_unused ret;
+	int ret;
+
+	ret = riscv_cpu_probe(ctx, event);
+	if (ret)
+		return ret;
 
 	/* Enable FPU */
 	if (supports_extension('d') || supports_extension('f')) {
@@ -141,7 +145,7 @@ int riscv_cpu_setup(void)
 
 	return 0;
 }
-EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
+EVENT_SPY_FULL(EVT_DM_POST_INIT_F, riscv_cpu_setup);
 
 int arch_early_init_r(void)
 {
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index 87a804bfd5..ffa7649f3f 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -26,6 +26,6 @@ struct event;
     } while (0)
 
 /* Hook to set up the CPU (called from SPL too) */
-int riscv_cpu_setup(void);
+int riscv_cpu_setup(void *ctx, struct event *event);
 
 #endif	/* __ASM_RISCV_SYSTEM_H */
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index 9a7a4f6ac8..c689398965 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -27,7 +27,7 @@ __weak void board_init_f(ulong dummy)
 	if (ret)
 		panic("spl_early_init() failed: %d\n", ret);
 
-	riscv_cpu_setup();
+	riscv_cpu_setup(NULL, NULL);
 
 	preloader_console_init();